1. Field of the Invention
The present invention relates to synchronous semiconductor memory devices and, more particularly, to a synchronous semiconductor memory device incorporating external signals including a control signal, an address signal, and a data signal in synchronization with an external clock signal.
2. Description of the Background Art
Although a dynamic random access memory (hereinafter referred to as a DRAM) used as a main memory operates at an increased speed, the operation speed thereof still cannot catch up with operation speed of a microprocessor (hereinafter referred to as MPU). Therefore, it has been often stated that access time and cycle time of a DRAM are bottleneck thereof to result in lower performance of the entire system. In recent years, a proposal is made to use a synchronous DRAM (hereinafter referred to as SDRAM) operating in synchronization with a clock signal as a main memory for a high speed MPU.
A specification of an SDRAM is proposed in which a high speed access is made to successive bits, for example successive 8 bits, for one data input/output terminal in synchronization with a system clock signal. A standard timing chart satisfying such specification of successive access is shown in FIG. 28. FIG. 28 shows operation of reading out data of 8 bits successively in an SDRAM that can input and output data of 8 bits (1 byte) at data input/output terminals DQ0 to DQ7. That is, data of 64 bits (8 bits.times.8=64 bits) can be written successively.
The number of bits of data to be read out or written successively is called a burst length, which can be changed by a mode register in an SDRAM.
As shown in FIG. 28, external control signals such as a row address strobe signal /RAS, a column address strobe signal /CAS, and an address signal Add are incorporated at a rising edge of an external clock signal CLK serving as a system clock in an SDRAM.
Address signal Add includes a row address signal Xa and a column address signal Yb multiplexed in a time-divisional manner.
At a rising edge of clock signal CLK in cycle 1, when an external row address strobe signal ext./RAS is activated at an "L" (Low) level and an external column address strobe signal ext./CAS and an external write enable signal ext./WE are at "H" (High) level, address signal Add applied at this point in time is incorporated as row address signal Xa.
Next, at a rising edge of clock signal CLK in cycle 4, when external column address strobe signal ext./CAS is activated at an "L" level, address signal Add applied at this point in time is incorporated as a column address signal Yb. Row and column selecting operation is carried out in the SDRAM in accordance with the incorporated row address signal Xa and column address signal Yb. After a predetermined clock period (6 clock cycles in FIG. 28) has been elapsed from the fall of external row address strobe signal ext./RAS to an "L" level, first data b0 of the 8-bit data to be output from data input/output terminal DQ is applied. Thereafter, data b1-b7 are applied in response to the rise of clock signal CLK.
FIG. 29 is a timing chart showing the state of the external signals when 8-bit data is written successively for one data input/output terminal DQ in an SDRAM.
In writing operation, row address signal Xa is incorporated similarly to data readout. More specifically, when signal ext./RAS is activated at an "L" level and signals ext./CAS and ext./WE are at an "H" level at the rising edge of clock signal CLK in cycle 1, address signal Add applied at this point in time is incorporated as row address signal Xa. At the rising edge of clock signal CLK in cycle 4, when signals ext./CAS and ext./WE are activated at an "L" level, column address signal Yb is incorporated and data b0 applied to data input/output terminal DQ at this point in time is incorporated as the first write data of the 8-bit data to be written successively. In response to the rising edges of signals ext./RAS and ext./CAS, row and column selecting operation is carried out in the SDRAM. Thereafter, in synchronization with clock signal CLK, input data b1-b7 is incorporated and written in the corresponding memory cells sequentially.
As described above, in contrast to the method of incorporating for operation an address signal, input data, and the like in synchronization with external control signals of row address signal ext./RAS and column address strobe signal ext./CAS in a conventional DRAM, external signals such as address strobe signals ext./RAS and ext./CAS, an address signal and input data are incorporated at the rising edge of clock signal CLK, which is an externally applied system clock, in an SDRAM.
Thus, an SDRAM performs operation of incorporating the control signal and the data signal in synchronization with the external clock signal, thereby eliminating the need for securing a margin for data input/output time in view of skew (a lag in timing) of the address signal. As a result, cycle time can be advantageously reduced. Thus, since successive data can be written and read out in synchronization with the clock signal, access time for making successive access to successive addresses can be reduced.
Choi et al. has presented a 2-bit prefetch SDRAM for writing data of 2 bits as one unit as an architecture for implementing an SDRAM (in 1993 Symposium on VLSI circuit). Description of the 2-bit prefetch operation will be described hereinafter with reference to the drawing.
FIG. 30 functionally shows the structure of a main part of a conventional SDRAM performing 2-bit prefetch operation. Referring to FIG. 30, the structure of a functional portion related to 1-bit input/output data in the SDRAM with x8 bit structure An array portion related to a data input/output terminal DQi includes a memory cell array 71a forming a bank A and a memory cell array 71b forming a memory array bank B. Banks A and B can be accessed independently.
Memory cell array bank A is further divided into memory cell array banks A0 and A1. Determination as to whether write data is written in memory cell array bank A0 or memory cell array bank A1 is made in accordance with the value of the least significant bit of the address applied when the write command is input.
Similarly, when memory cell array bank B is selected, determination as to whether write data is written in memory cell array bank B0 or memory cell array bank B1 is made in accordance with the least significant bit of the address applied when the write command is input.
Memory cell array banks A0 and A1 are each provided with an X decoder group 52a including a plurality of row decoders each decoding address signals X0-Xj and selecting a corresponding row of memory cell array 71a, a Y decoder group 53a including a plurality of column decoders each decoding column address signals Y1-Yk and selecting a corresponding column of memory cell array 71a, and a sense amplifier group 54a for detecting and amplifying data of the memory cells connected to the selected row in memory cell array group 71a.
Memory cell array banks A0 and A1 are further provided with an internal data transmission line (global I/O line) for transmitting the data detected and amplified by sense amplifier group 54a and transmitting write data to the selected memory cell of memory cell array 71a. A write register 59a and a write buffer group 60a are provided corresponding to a global I/O line pair GIO0 which corresponds to memory cell array bank A0, and a write register 59a' and a write buffer group 60a' are provided corresponding to a global I/O line pair GIO1 which corresponds to memory cell array bank A1. A selector 69a for switching an output of an input buffer 58a to be applied to two write registers 59a and 59a' in accordance with the value of the least significant bit of the address applied when the write command is applied. An equalizing circuit group 61a is provided common to the two global I/O line pairs GIO0 and GIO1.
Another set of circuits similar to those in memory cell array bank A is provided in memory cell array bank B. Since description below will be made of operation of the SDRAM focusing on write operation thereof, FIG. 30 shows only the structure of the circuits related to writing.
Now, brief description will be made of operation of the conventional SDRAM shown in FIG. 30. FIG. 31 is a timing chart describing write operation of the conventional SDRAM. Description below relates to an example where the value of a low order address is "0", the burst length equals to 4 and data is written in bank A. In other words, successive 4-bit data is written in memory cell bank A.
In FIG. 31 as well, an arbitrary one of data input/output terminals is represented as DQ. At the rising edge of external clock signal ext.CLK in cycle 1, in response to external column address strobe signal ext./CAS being activated at an "L" level, column address signal Yb is incorporated and a corresponding Y decoder is activated. More specifically, a column selection signal .phi.CSL0 corresponding to a selected column in Y decoder group A0 and a column selection signal .phi.CSL1 corresponding to a selected memory cell column in Y decoder group A1 change to an "H" level in an activated state.
At the rising edge of clock signal ext.CLK in cycle 1, the first data d0 applied to data input/output terminal DQ is stored in write register 59a, and then data d0 stored in write register 59a is applied to global I/O line pair GIO0 in response to activation of a write buffer activation signal .phi.WBA0 output from a second control signal generation circuit 63. The data applied to global I/O line pair GIO0 is written in a corresponding memory cell in the memory cell column selected by column selection signal .phi.CSL0.
At the rising edge of external clock signal ext.CLK in cycle 2, data d1 is incorporated from data input/output terminal DQ and stored in write register 59a'. In response to activation of a write buffer activation signal .phi.WBA1 applied from second control signal generation circuit 63, data d1 is output to global I/O line pair GIO1. Data d1 is also written in a corresponding memory cell in a column selected by a signal .phi.CSL1.
In the manner described above, data of 2 bits is written and after completion thereof write buffer activation signals .phi.WBA0 and .phi.WBA1 are both inactivated. As a result, write registers 59a and 59a' are electrically disconnected from global I/O line pairs GIO0 and GIO1.
In response to the rising edge of external clock signal ext.CLK in cycle 3, an equalize signal .phi.WEQA is applied from second control signal generation circuit 63, and in response thereto equalizing circuit 61a equalizes global I/O line pairs GIO0 and GIO1 connecting memory cell array banks A0 and A1 and write buffer groups 60a and 60a', respectively.
In response to the rising edge of signal ext.CLK in cycle 3, data d2 applied to data input/output terminal DQ is incorporated and stored in write register 59a. Furthermore, in response to the rising edge of signal ext.CLK in cycle 3, a column selection signal .phi.CSL2 selecting a memory cell column including a memory cell to which data is next written in memory cell array bank A0 and a column selection signal .phi.CSL3 selecting a memory cell column including a memory cell to which data is next written in memory cell array bank A1 are activated (attaining an "H" level). Thus, in response to activation of write buffer activation signal .phi.WBA0, data d2 is written in the corresponding memory cell in memory cell array bank A0.
At the rising edge of signal ext.CLK in cycle 4, data d3 is next incorporated and stored in write register 59a'. In response to activation of write buffer activation signal .phi.WBA1, data d3 is written in a corresponding memory cell in memory cell array bank A1.
Thus, the SDRAM performing 2-bit prefetch operation writes data every 2 clock cycles, and therefore sufficient time can be taken for data writing even if the external clock signal has an increased frequency, thereby easily achieving increase in operation frequency.
However, during the 2-bit prefetch operation of the conventional SDRAM described above, in the cycle when writing operation is performed for a head data (data of the first bit to be written), the memory cell column to which data of the second bit is to be written is selected simultaneously and connected with an I/O line pair. Therefore, the potential of the I/O line pair used for writing the data of the second bit is changed, in accordance with the data held previously in the memory cell where the data of the second bit is to be written, in the cycle when the data of the first bit is written. As a result, in the cycle for writing the data of the second bit, the potential of the I/O line pair having a complementary structure must be inverted if the data opposite to the data held previously is to be written.
Extra time is required for inversion of the potential of the I/O line pair with a great stray capacitance, causing increase in time for writing and degradation in operable frequency.